This application relates to integrated circuits, and more particularly, to methods in which to diagnose and rectify yield issues when a new design is introduced on a new process.
Structured application specific integrated circuits (ASIC) are integrated circuit devices that include predefined layers, a large portion of which can be configured to implement random logic. Random logic can be characterized as a sea of combinatorial logic and sequential elements. The random logic can be efficiently integrated into a customer design by combining the different unit logic elements within the random logic. Defects in the structured ASIC can occur anywhere. In case of the predefined layers, the defects can occur in the random logic section or in other sections. To diagnose and cure defects in the random logic section can be harder than to diagnose and cure defects in other portions of the structured ASIC. For example, defects are easier to diagnose in memory blocks due to their regularity.
Currently, integrated circuits (ICs) are tested using automatic test pattern generator (ATPG) programs. ATPG programs generate test vectors, which are driven through a test scheme known as a scan design. Scan designs move test vectors in a serial manner. The test vectors are initially captured in scan chains and then forwarded through the logic to be tested and the test results are captured in registers. Scan chains are generally defined by numerous shift registers. As this type of testing depends on the test vector, the type of defect, and other variables, this type of testing is not very effective in pinpointing defects in the case of random logic.
As a result, there is a need to be able to diagnose and rectify defects in random logic rapidly.